[erlang-questions] Erlang on RISC-V

[Mikael Pettersson]

On Fri, May 11, 2018 at 3:15 PM, Mikael Karlsson <karlsson.rm@REDACTED> wrote:
>>It's not clear there is any need, since the BEAM should work as-is.
>
> Yes, the Fedora port you pointed out has already an Erlang port.
>
> However the RISC-V is a register machine (as the Erlang VM) with 32 integer
> registers so I wonder it there are any optimizations that may be done.
> I can see in the beam_emu.c a can see for other architectures sections like:
> /*
>  * On certain platforms, make sure that the main variables really are placed
>  * in registers.
>  */
> ..
> #elif defined(__GNUC__) && defined(__amd64__) && !defined(DEBUG)
> #  define REG_xregs asm("%r12")
> #  define REG_htop
> #  define REG_stop asm("%r13")
> #  define REG_I asm("%rbx")
> #  define REG_fcalls asm("%r14")
> #else
> ..
> The RISC-V assembly programmer's handbook lists registers as (chapter 20 in
> the spec):
> Register ABI Name Description Saver
> x0 zero Hard-wired zero |
> x1 ra Return address Caller
> x2 sp Stack pointer Callee
> x3 gp Global pointer |
> x4 tp Thread pointer |
> x5 t0 Temporary/alternate link register Caller
> x6-7 t1-2 Temporaries Caller
> x8 s0/fp Saved register/frame pointer Callee
> x9 s1 Saved register Callee
> x10-11 a0-1 Function arguments/return values Caller
> x12-17 a2-7 Function arguments Caller
> x18-27 s2-11 Saved registers Callee
> x28-31 t3-6 Temporaries Caller
>
> So I guess some similar "reservations" can be made for RISC-V as for amd64,
> but I am not sure how to map them here.

This can be done of course.  The code reserves callee-save registers
for important
BEAM VM variables on SPARC and AMD64, so you should identify 5 callee-save
registers in the RISC-V ABI and bind them in a similar way.  Your list
is a bit unclear,
but I guess the s0-s11 registers are callee-save; pick say the last 5.

It's probably not worth trying to bind even more BEAM VM variables to
registers, as
that means more work in transitions in to and out of process_main().

You'll want to run the estone SUITE to see how much of a difference
register variables
make on RISC-V.

/Mikael