[erlang-questions] Erlang on RISC-V

[Mikael Karlsson]

2018-02-20 14:45 GMT+01:00 Mikael Pettersson <mikpelinux@REDACTED>:

> On Tue, Feb 20, 2018 at 11:49 AM, Matthias Lang <matthias@REDACTED>
> wrote:
> > On 19. February 2018, Mikael Karlsson wrote:
> >
> >> has anyone looked at having the Erlang compiler support RISC-V,
> >
> > I haven't.
> >
> > What do you mean by "the Erlang compiler"?
> >
> > The regular Erlang compiler, i.e. the one that generates .beam files,
> > generates .beam files which don't care what CPU you want to run on.
> >
> > HiPE is a different story, but you didn't mention HiPE.
>
> RISC-V support in HiPE should be straight-forward, but no-one is
> working on that AFAIK.
> It's not clear there is any need, since the BEAM should work as-is.
>
> There is also that HiPE/LLVM thing which might be able to support RISC-V
> with less effort.
>
> > Getting the VM to run is another task, though once people have linux
> > and a toolchain running (I see that there's an active debian effort,
> > for instance), I would expect that to be the same level of difficulty
> > as compiling on, say, MIPS linux for the first time---i.e. maybe it'll
> > just work, maybe you have to do a bit of autotools fiddling.
>
> RISC-V has full GNU/Linux support with latest GCC, binutils, GLIBC,
> and Linux kernel, and I know both Debian and Fedora have started ports.
> But you don't need to wait for a full distro port, all you need is a
> cross-compiler
> and busybox or sth and you're done.
>
> > The mention of RISC-V just made me think, "I haven't heard anything
> > about Tilera for a while". I think it's been a few years since anyone
> > here said anything about it on the mailing list. Anyone know if it's
> > still alive?
>
> Tilera is dropping their Tile processors and migrating to some other core
> (I don't know which one, but probably ARM or MIPS.)  See e.g. their recent
> announcements to drop the older TilePro from Linux and glibc, keeping only
> Tile-Gx due to some customers still using it.
>

Hi again Mikael,

>It's not clear there is any need, since the BEAM should work as-is.

Yes, the Fedora port you pointed out has already an Erlang port.

However the RISC-V is a register machine (as the Erlang VM) with 32 integer
registers so I wonder it there are any optimizations that may be done.
I can see in the beam_emu.c a can see for other architectures sections like:
/*
 * On certain platforms, make sure that the main variables really are placed
 * in registers.
 */
..
#elif defined(__GNUC__) && defined(__amd64__) && !defined(DEBUG)
#  define REG_xregs asm("%r12")
#  define REG_htop
#  define REG_stop asm("%r13")
#  define REG_I asm("%rbx")
#  define REG_fcalls asm("%r14")
#else
..
The RISC-V assembly programmer's handbook lists registers as (chapter 20 in
the spec):
Register ABI Name Description Saver
x0 zero Hard-wired zero |
x1 ra Return address Caller
x2 sp Stack pointer Callee
x3 gp Global pointer |
x4 tp Thread pointer |
x5 t0 Temporary/alternate link register Caller
x6-7 t1-2 Temporaries Caller
x8 s0/fp Saved register/frame pointer Callee
x9 s1 Saved register Callee
x10-11 a0-1 Function arguments/return values Caller
x12-17 a2-7 Function arguments Caller
x18-27 s2-11 Saved registers Callee
x28-31 t3-6 Temporaries Caller

So I guess some similar "reservations" can be made for RISC-V as for amd64,
but I am not sure how to map them here.

Best Regards
Mikael K
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