[erlang-questions] Erlang on RISC-V

[Mikael Karlsson]

2018-05-11 18:52 GMT+02:00 Mikael Pettersson <mikpelinux@REDACTED>:
>
> On Fri, May 11, 2018 at 3:15 PM, Mikael Karlsson <karlsson.rm@REDACTED> wrote:
> >>It's not clear there is any need, since the BEAM should work as-is.
> >
> > Yes, the Fedora port you pointed out has already an Erlang port.
> >
> > However the RISC-V is a register machine (as the Erlang VM) with 32 integer
> > registers so I wonder it there are any optimizations that may be done.
> ...
>
> > So I guess some similar "reservations" can be made for RISC-V as for amd64,
> > but I am not sure how to map them here.
>
> This can be done of course.  The code reserves callee-save registers for important
> BEAM VM variables on SPARC and AMD64, so you should identify 5 callee-save
> registers in the RISC-V ABI and bind them in a similar way.  Your list is a bit unclear,
> but I guess the s0-s11 registers are callee-save; pick say the last 5.
>
> It's probably not worth trying to bind even more BEAM VM variables to
> registers, as that means more work in transitions in to and out of process_main().
>
> You'll want to run the estone SUITE to see how much of a difference
> register variables make on RISC-V.

Great,

many thanks for the info.

Also for anyone interested the last RISC-V workshop just finished in Barcelona,
https://riscv.org/2018/04/risc-v-workshop-in-barcelona-agenda/

/Mikael K