CPU/Hardware optimized for Erlang

[David Hopwood]

Will Newton wrote:
> On Monday 25 July 2005 10:20, Thomas Lindgren wrote:
> 
>>I don't think this is a big handicap. Yes, it leads to
>>extra complexity, but high-performance hardware
>>already is very complex (as I'm sure you know). The
>>instruction set or legacy features of IA32 really
>>doesn't seem to be the bottleneck when you look at the
>>results.
> 
> I don't have any hard numbers of course (this is the Internet after all), but 
> I would imagine that the number of transistors required to implement the wide 
> array of instructions in such a chip limits the possibilities of putting more 
> cores on a die because eventually your power dissipation will become a 
> problem.

It occurs to me that it might be useful to have only one core that is
x86-compatible, and the rest using an architecture that can be optimized
for die area and power dissipation without being constrained by backward
compatibility. (In fact, the Cell processor is not too dissimilar to this,
with PPC instead of x86.)

-- 
David Hopwood <david.nospam.hopwood@REDACTED>