CPU/Hardware optimized for Erlang
Tue Jul 26 11:21:54 CEST 2005
--- Will Newton <> wrote:
> I don't have any hard numbers of course (this is the
> Internet after all), but
> I would imagine that the number of transistors
> required to implement the wide
> array of instructions in such a chip limits the
> possibilities of putting more
> cores on a die because eventually your power
> dissipation will become a
Note that after decoding, the CISC instructions have
been translated to uops, traces of uops, or what have
you. I believe the difference with a RISC is small
after that point.
I also think other architectural features are more
costly at this time, e.g., big branch predictors,
large multiported register files, large instruction
windows, fast clock ...
I'll have a peek :-)
> Are you aware of any overviews of this processor
The APZ family run the Ericsson AXE switches, and are
programmed in PLEX. Lots of features will be
recognized by Erlang programmers.
While they are getting a bit long in the tooth (even
pre-2000, I heard of multiple efforts to write
emulators and JITs to get rid of them) they have had
at least a 20-year run. When I left Ericsson, pre-2K,
there were tens of thousands of people working with
AXE and PLEX.
Here's a sample article:
I think ericsson.com has a bit more info if you
rummage around. (Presumably, there are also *plenty*
of readers on this list who do :-)
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