CPU/Hardware optimized for Erlang

Will Newton <>
Mon Jul 25 19:46:46 CEST 2005

On Monday 25 July 2005 10:20, Thomas Lindgren wrote:

> I don't think this is a big handicap. Yes, it leads to
> extra complexity, but high-performance hardware
> already is very complex (as I'm sure you know). The
> instruction set or legacy features of IA32 really
> doesn't seem to be the bottleneck when you look at the
> results.

I don't have any hard numbers of course (this is the Internet after all), but 
I would imagine that the number of transistors required to implement the wide 
array of instructions in such a chip limits the possibilities of putting more 
cores on a die because eventually your power dissipation will become a 

> > If you have a specific load (e.g. floating point,
> > integer, I/O, DSP, highly
> > concurrent) it is not that difficult to build a chip
> > that is faster than a
> > more general purpose processor.
> I agree -- my recommendation thus remains: optimize
> the hardware for the application, not the language :-)

The processor I am working on tries to take that approach:


> In the case of Erlang-in-telecoms, perhaps the APZ
> processor could be a fine source of inspiration (it's
> certainly a very successful product line).

Are you aware of any overviews of this processor architecture?

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