[erlang-questions] Executing Erlang on a FPGA (Re: How small could an Erlang emulator be?)
Sun Mar 18 04:01:50 CET 2007
On 16-Mar-07, at 10:29 PM, Roger Larsson wrote:
> On Thursday 15 March 2007 20:42, Toby Thain wrote:
>> On 15-Mar-07, at 3:02 PM, Vance Shipley wrote:
>>> I recall that someone made the suggestion on this list that
>>> the Crusoe processor, being softwaree definable, could be
>>> turned into an Erlang processor. It's just software. :)
>> Or soft CPU on FPGA.
> Yes, I have also thought about that.
> Would be an interesting project!
> [Lots of interesting research areas
> - what "CPU" model to use:
> JAM, beam, Icode, special purpose, extended general purpose
> - hardware assisted memory allocation
> + write queue with single assignment optimizations and reference
> - hardware assisted garbage collection
> - hardware assisted operating systems
> see http://www.xilinx.com/publications/magazines/emb_02/xc_pdf/
> and/or "Programmerbara kretsar" ISBN 91-44-03713-9
> Sierra has been sold to Prevas - see
> - hardware assisted serialization (for communicating with the host
> - hardware assisted message sending (scatter gather DMA but data
> contains the links)
> - ...
> Who does this already?
The Transputer had hardware process timeslicing, blocking and message
passing... Has anyone considered what kind of fit Erlang would be to
There is a Transputer-inspired CPU being worked on by John Jakson:
He also wrote a nice introduction to the Transputer concept:
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