Erlang on Tilera

Mon Jun 15 16:06:56 CEST 2009

Hello list,

After having seen Kenneth Lundin's post about the Erlang SMP VM running on 
a 64 core Tilera and the README files of R13A and R13B01, we could be 
interested in giving these architectures a try.

Would it be possible to have more information regarding the actual 
hardware that was tested with Erlang (processor: TilePro64?, card: 
TileExpress/TileEncore/other?), the procedure that you followed (ex: to 
cross-compile an Erlang VM, to select the number of nodes being used, 
etc.) and your overall feeling about this architecture?

Thanks in advance for any information,
Best regards,

Olivier Boudeville.
Olivier Boudeville

EDF R&D : 1, avenue du Général de Gaulle, 92140 Clamart, France
Département SINETICS, groupe ASICS (I2A), bureau B-226
Office : +33 1 47 65 59 58 / Mobile : +33 6 16 83 37 22 / Fax : +33 1 47 
65 27 13

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