[erlang-questions] http://en.wikipedia.org/wiki/Intel_iAPX_432#Multitasking_and_interprocess_communication

Martin Scholl <>
Thu Dec 3 10:54:31 CET 2009


Michael Turner wrote:
> Intel architecture per core, with (unstated but necessarily) limited
> memory per core, and no cache coherence . . . well, this just leaves me
> asking: Why bother with Intel architecture per core?  All it gets you is
> binary compatibility with apps written for Intel CPUs, and just about
> everything already written for Intel CPUs requires a large virtual
> address space these days.
Actually, there is a an operating system written to handle this:
Barrelfish[0].
Why does this arch have no cache coherent shared memory? In [1] you will
find arguments why a low-level rpc / message passing system actually
outperforms shared-memory based communication given a sufficient large
number of cores / dies / cpus.

> 
> Just about any RISC architecture would probably consume less area and
> power per core.  ARM cores, for example, would make a lot more sense. 
> Not likely to see that from Intel, though.
True. But ARM is getting traction in large-scale deployment. E.g. Dell
has an offering based on low-cost low-power ARM-based "microslice" servers.


Martin

[0] http://barrelfish.org/
[1] http://barrelfish.org/barrelfish_sosp09.pdf


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