Thu Dec 3 09:04:17 CET 2009
Intel architecture per core, with (unstated but necessarily) limited
memory per core, and no cache coherence . . . well, this just leaves me
asking: Why bother with Intel architecture per core? All it gets you is
binary compatibility with apps written for Intel CPUs, and just about
everything already written for Intel CPUs requires a large virtual
address space these days.
Just about any RISC architecture would probably consume less area and
power per core. ARM cores, for example, would make a lot more sense.
Not likely to see that from Intel, though.
Intel's Justin Rattner (the CTO quoted in the article) and message
passing architectures actually have some shared history. Under his
direction, Intel R&D probably implemented something like Erlang
messaging in silicon as far back as 1981:
But not just message passing and h/w support for concurrency and
parallelism, but on-chip object-orientation and garbage collection as
These people know how to do everything, and they have known how for a
long time. But once you get them started, they just don't know where
On 12/2/2009, "Richard Andrews" <> wrote:
>I found the parallels between this chip's message passing system and
>the erlang inter-process messaging interesting. In some ways it's a
>validation of the core ideas in erlang about how to scale for truly
>concurrent operations - eg. share nothing, pass messages.
>How well do you think erlang would run on this architecture?
>erlang-questions mailing list. See http://www.erlang.org/faq.html
>erlang-questions (at) erlang.org
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