[erlang-questions] Executing Erlang on a FPGA (Re: How small could an Erlang emulator be?)
Sat Mar 17 02:29:34 CET 2007
On Thursday 15 March 2007 20:42, Toby Thain wrote:
> On 15-Mar-07, at 3:02 PM, Vance Shipley wrote:
> > I recall that someone made the suggestion on this list that
> > the Crusoe processor, being softwaree definable, could be
> > turned into an Erlang processor. It's just software. :)
> Or soft CPU on FPGA.
Yes, I have also thought about that.
Would be an interesting project!
[Lots of interesting research areas
- what "CPU" model to use:
JAM, beam, Icode, special purpose, extended general purpose
- hardware assisted memory allocation
+ write queue with single assignment optimizations and reference counting?
- hardware assisted garbage collection
- hardware assisted operating systems
and/or "Programmerbara kretsar" ISBN 91-44-03713-9
Sierra has been sold to Prevas - see
- hardware assisted serialization (for communicating with the host CPU)
- hardware assisted message sending (scatter gather DMA but data itself
contains the links)
Who does this already?
 Extended general purpose
Generate Sparc executable, add whatever instruction needed. Possible since Sun
have released their 64-bit SPARC V9 as GPL http://opensparc-t1.sunsource.net/
"The OpenSPARC T1 processor contains eight SPARC® processor cores, which each
have full hardware support for four threads. Each SPARC core has an
instruction cache, a data cache, and a fully associative instruction and data
translation lookaside buffers (TLB). The eight SPARC cores are connected
through a crossbar to an on-chip unified level 2 cache (L2-cache)."
Difficult to fit on a FPGA, but there is hope :-)
http://www.opencores.org/projects.cgi/web/s1_core/overview (modified T1)
"one 64-bit SPARC v9 core (capable of running up to 4 concurrent threads)"
no cache, but with wishbone interface...
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