Fri Dec 4 10:35:00 CET 2009
On 12/4/2009, "Michael Richter" <ttmrichter@REDACTED> wrote:
>2009/12/3 Michael Turner <leap@REDACTED>
>> Just about any RISC architecture would probably consume less area and
>> power per core. ARM cores, for example, would make a lot more sense.
>> Not likely to see that from Intel, though.
>Intel wasn't always x86-only... <http://en.wikipedia.org/wiki/XScale>
Which kind of proves my point: they got a line of ARM-based IP from a
lawsuit settlement with DEC, only to dump that line later, on Marvell.
Admittedly, before that, they had their i860/960 RISC processors, even
their own workstations that used them. But I never got the impression
they were very serious about RISC on the product side. They didn't
have to be, really. Intel has deep pockets, they learn a lot about
competitive threats (and new markets within them) simply by emulating
industry trends in-house. Even if they lost money on the i860 and the
workstation they cobbled together around it, they probably learned
something very valuable: how to make money in the market for support
chips for engineering workstations. In any market-based view of the
matter, however, anything RISCy is risky -- mainly, cannibalistic -- for
I think Erlang is more likely to have an impact sometime soon in
massive-multicore apps IF it can become popular as some sort of
higher-level control language for specialized processor arrays, such as
the kind suggested here (in another response to the Intel announcement):
Researchers rethink approaches to computer vision
Not just in the lab, either. For apps with a (relatively) fixed process
structure, Erlang programs might, with modifications, be mapped onto
systems like the picoArray
Note that typical applications for picoArrays (cellular basestations) are
also conveniently adjacent to the telecom equipment where Erlang earned
its spurs industrially.
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