[erlang-questions] Tilera 64-core chip

Thomas Lindgren thomasl_erlang@REDACTED
Mon Aug 20 16:15:47 CEST 2007

--- "Ulf Wiger (TN/EAB)" <ulf.wiger@REDACTED>

> Does anyone have experience with Tilera?
> http://www.tilera.com/index.php
> For example their PCI Express card with a 64-core*
> chip
> and 6-12 gigabit Ethernet ports, all running at ca
> 35W,
> sounds like a pretty good match for SMP Erlang... (:

It does seem to run Linux (in some sense, "supports"
is a flexible word) so it can't be too exotic. That's
good. I wonder what ISA the cores implement? MIPS?
PPC? It also seems interesting to consider this:

1. 5MB onchip cache => 78 KB per core (at a guess
that's 16+64 KB locally per core in split caches of
some sort).

2. What memory bandwidth does the chip support? (E.g.,
how many pins?) And what will 64 SMP Erlang cores


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