[erlang-questions] FPGA coming around the corner

[James Churchman]

How much of the average erlang code spends its cpu time siting in BIF's and
how much is the erlang code its self? (and does this
change significantly with HiPE??)

Im assuming its not a significant amount of time, but if it is should be
posible to produce a set of some of the bifs for an FPGA

Been a few years now but had to do a moderate amount of VHDL for FPGA's at
uni, tho i hear good things about Bluespec, its bassed on haskell and is
also a hardware description language


james

On 9 January 2011 14:25, Ulf Wiger <ulf.wiger@REDACTED> wrote:

>
> On 7 Jan 2011, at 07:44, Edmond Begumisa wrote:
>
> > But that's precisely what these advocates are warning their audiences
> about! That the *legacy apps and code will have to be re-written* in order
> to be parallelised for multi-core. That's what the panic is about. That
> these programs and libraries will need to be carefully re-coded using lots
> of threads, concurrent data structures and unfamiliar paradigms like
> "transactional boosting."
> >
> > The Herlihy's are effectively saying: "You will need to re-write you're
> apps and libs in order for your users not to complain that things are
> slower, and here's a bunch of tools you can use that we *hope* will make it
> a little easier. But it will still be pretty hard."
>
>
> Actually achieving scalability on multicore is only one of the tough
> challenges facing legacy software developers; *debugging* shared-
> memory imperative applications on multicore is essentially a research
> area.
>
> BR,
> Ulf W
>
> Ulf Wiger, CTO, Erlang Solutions, Ltd.
> http://erlang-solutions.com
>
>
>
>
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