[erlang-questions] HiPE on MIPS/MIPS-64
Tue May 1 13:38:40 CEST 2007
On Mon, 30 Apr 2007 12:49:17 -1000, Jim Thompson wrote:
> I'm interested in discussing what it would take to get MIPS/MIPS-64
> support into HiPE. HiPE already supports SPARC (32 & 64bit), PPC (32 &
> 64 bit) and x86 (as well as x86-64).
HiPE doesn't support SPARC64 or PPC64 user-mode; it does support
SPARC32 and PPC32 user-mode on both 32- and 64-bit kernels.
A PPC64 project was started but never completed due to us not having
a PPC64 machine. It would be easy to complete, though.
HiPE also supports XScale, Intel's ARM processor.
> I've read that the internal RLT for HiPE looks a lot like the MIPS
> instruction set.
> Is it just a matter of defining (or re-using) the ABI for the platform,
> and then writing the 'glue' for plugging the binary, or is it much, much
> more complex that that?
I had a look at supporting MIPS in HiPE last year, and from what I remember,
it would be straightforward except for a few issues:
- MIPS has no condition codes. This makes overflow in arithmetic difficult
to detect. I'm not sure if this can be hidden completely in the backend
or if it will need some hooks in RTL.
- MIPS partitions the memory into 256MB regions, and direct branches can
only reach targets in the same region. The consequence is that branches
between regions must be routed via trampolines containing indirect jumps.
HiPE already uses trampolines on PPC32 and ARM, so this is doable. It
does add complexity to the runtime system and the code loader, however.
- If hardware floating-point is to be used, then you'll need to first
port the base BEAM runtime system to use floating-point exceptions.
> Yes, this is with an Octeon chipset in-mind (16 cores, discussed on-list
> last August), seems like an ideal 1U Erlang box to me.
> Also, why no SPARC-on-Intel support for HiPE?
HiPE worked just fine on Solaris/x86 and Solaris/amd64
last time I checked.
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