[erlang-questions] HiPE on MIPS/MIPS-64

[Jim Thompson]

I'm interested in discussing what it would take to get MIPS/MIPS-64 
support into HiPE.   HiPE already supports SPARC (32 & 64bit), PPC (32 & 
64 bit) and x86 (as well as x86-64).

I've read that the internal RLT for HiPE looks a lot like the MIPS 
instruction set.

Is it just a matter of defining (or re-using) the ABI for the platform, 
and then writing the 'glue' for plugging the binary, or is it much, much 
more complex that that?

Yes, this is with an Octeon chipset in-mind (16 cores, discussed on-list 
last August), seems like an ideal 1U Erlang box to me.

Also, why no SPARC-on-Intel support for HiPE?

Jim